RTS: Add missing memory barrier

Authored by trommler on Feb 24 2019, 10:11 AM.

Description

RTS: Add missing memory barrier

In the work stealing queue a load-load-barrier is required to ensure
that a read of queue data cannot be reordered before a read of the
bottom pointer into the queue.

The added load-load-barrier ensures that the ordering of writes enforced
at the end of pushWSDeque is also respected in the order of reads in
stealWSDeque_. In other words, when reading q->bottom we want to make
sure that we see the updates to q->elements.

Fixes Trac #13633

(cherry picked from commit 5c084e0468be46f5ab48b2c1669a7e4d4d0f3c43)

Details

Committed
bgamariJun 17 2019, 4:20 PM
Parents
rGHC61e13e06d7e1: users-guide: Move HIE file discussion to correct section
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