- User Since
- Jun 6 2014, 3:56 PM (227 w, 4 d)
Mon, Oct 8
I was hoping the fix would help with Trac #15411 but it doesn't. So I removed the reference to that ticket.
Sun, Oct 7
Aug 21 2018
Perhaps we can avoid negation and say what the guarantee of the barrier actually is.
Aug 3 2018
My comment was meant as a contribution of an idea to the discussion. Sorry, I should have made that explicit.
Aug 1 2018
Linux documentation of memory barriers defines a write barrier as follows:
Jul 25 2018
Jul 22 2018
Jun 10 2018
- Expand tabs.
May 26 2018
Mar 9 2018
Note: I don't have a working SPARC machine so I could not test this.
Mar 5 2018
I created D4468 for this.
Feb 1 2018
I think atomic read is fine but atomic write is missing a parameter. See inline comment.
Currently MO_SS_Conv W32 W64 is not supported on 32 bit PPC. In fact, we would get a compiler panic if I understand the code in nativeGen/PPC/Codegen.hs right.
Nov 27 2017
I have a small comment regarding the C functions.
Nov 14 2017
LGTM. I validated this diff applied to HEAD and Phab:D4181 on a POWER8 (powerpc64-linux) with no regressions.
Nov 12 2017
I built the diff against HEAD on a POWER8 and got this error:
Nov 6 2017
Nov 5 2017
- Improve comments
- Fix duplicate labels on powerpc64le
Nov 4 2017
I'd like to fix powerpc64le, too.
- Break up long lines
- Make block info tables local and simplify
- Simplify and always use infoTblLbl
- Add note Proc-point block entry-point
Nov 3 2017
Nov 2 2017
Oct 2 2017
Sep 30 2017
- add lost commit
- add comment for memory barrier
Sep 27 2017
For atomic read the answer is yes.
Sep 23 2017
I checked the POWER ISA docs and compared the code with what gcc does. I also added a comment with references to the POWER docs in a place where the code looks very odd.
- add comments and fix typo
Sep 22 2017
Sep 17 2017
May 9 2017
Let's use Ben's patch D3560. It is both cleaner and more efficient.
Yes. That is better than my patch.
May 5 2017
Apr 30 2017
Apr 25 2017
Mar 27 2017
- Fix count trailing zeros formula in comment
Mar 25 2017
Mar 24 2017
Fix long lines.
Rebase again to fix Habormaster builds.
Mar 21 2017
Rebase so it applies cleanly to HEAD again.
Jan 17 2017
Jan 16 2017
Jan 14 2017
- Break up long lines
Dec 18 2016
- remove newline.
Dec 16 2016
- Fix typos in comment.
- Improve RTS linker support detection
- RTS linker: Better error message on PPC64
- RTS linker: Note runtime-linker-support
Dec 6 2016
Dec 5 2016
- Testsuite: rename config property
Dec 3 2016
I added a new property for runtime linker support to settings
- add to GHC info if RTS linker is supported
- Testsuite: skip another test when no RTS linker
- Fix typo.
Dec 2 2016
Dec 1 2016
Oct 11 2016
Inline comment done.
Oct 10 2016
- Move write barrier and add comment
Oct 6 2016
Sep 30 2016
- Add note referring to Power ISA specification
Sep 28 2016
Sep 25 2016
Sep 11 2016
Aug 7 2016
Aug 1 2016
Thank you Alex!
Jul 31 2016
Builds on PowerPC 64-bit now.
Jul 29 2016
This builds on PowerPC 64-bit big endian.
One macro is still AMD/Intel specific.
Please support all 64-bit platforms. See my inline comment.
Jul 28 2016
Jun 21 2016
Jun 13 2016
Please let me know if I need to add more information here.
- Improve comment.
- Explain why we need NOPs after a call.
Jun 12 2016
- untabify C file
Forgot the first commit (again) :-(
Jun 1 2016
May 27 2016
- update file path in comment
- Improve comments after code review.