- Fix for Trac #13904 -- stop "trashing" callee-saved registers, since it is not actually doing anything useful.
- Fix for Trac #14251 -- fixes the calling convention for functions passing raw SSE-register values by adding padding as needed to get the values in the right registers. This problem cropped up when some args were unused an dropped from the live list.
- Fixed a typo in 'readnone' attribute
- Added 'lower-expect' pass to level 0 LLVM optimization passes to improve block layout in LLVM for stack checks, etc.
make test WAYS=optllvm and make test WAYS=llvm
It turns out that the padding should be slightly different for AArch64, because we use a disjoint set of registers for float and double (although Sx and Dx registers on AArch64 still alias to the Vx register).
Basically, for AArch64 we need to first partition the set of live SSE regs into a float list and a double list, and pad those separately (with their respective type). I can upload a new revision doing this, but I don't know how to test on AArch64.