Add bit scan {forward,reverse} & CMOVcc insns to x86 NCG
ClosedPublic

Authored by hvr on Aug 11 2014, 5:41 AM.

Details

Summary

This is a pre-requisite for implementing count-{leading,trailing}-zero
prim-ops (re Trac #9340)

Test Plan

compiles and validates together with D144 which is based on the new insns

Diff Detail

Repository
rGHC Glasgow Haskell Compiler
Branch
master
Lint
Lint OK
Unit
No Unit Test Coverage
Build Status
Buildable 393
Build 394: GHC Patch Validation (amd64/Linux)
hvr updated this revision to Diff 317.Aug 11 2014, 5:41 AM
hvr retitled this revision from to Add bit scan {forward,reverse} insns to x86 NCG.
hvr updated this object.
hvr edited the test plan for this revision. (Show Details)
hvr added reviewers: ezyang, rwbarton, simonmar.
ezyang edited edge metadata.Aug 11 2014, 5:52 AM

Bugs

compiler/nativeGen/X86/Instr.hs
354

This is not right, dest is read from as well. Something like use_R dest $! use_R src [] should work

530

Since dst is read from, I'm not sure if this is correct now.

ezyang requested changes to this revision.Aug 11 2014, 5:53 AM
ezyang edited edge metadata.
This revision now requires changes to proceed.Aug 11 2014, 5:53 AM
hvr added inline comments.Aug 11 2014, 6:03 AM
compiler/nativeGen/X86/Instr.hs
354

Thanks, that fixed the register-allocation issues I saw; I've now changed that line to read

CMOV _ _ src dst    -> mkRU (use_R src [dst]) [dst]

and the code-generation works much better now.

530

...maybe @simonmar or @rwbarton could provide some guidance here? :-)

Yay! Build B385: Diff 317 (D141) has succeeded! Full logs available at F12372.

rwbarton edited edge metadata.Aug 11 2014, 8:20 AM

This LGTM. I only wonder if CMOV might fit better alongside SETCC, but it hardly matters.

compiler/nativeGen/X86/Instr.hs
354

Yes, this is right now. CMOV _ has the same usage pattern as, say, ADD, except that the destination must be a register. If you look at the definition of usageRM, when the destination is a register, it reduces to what you wrote above.

530

I believe the read/write usage pattern is irrelevant to this function, which is just about rewriting an instruction that operates on virtual registers to an instruction that operates on real registers once we have assigned real registers to those virtual registers. Basically the whole function is a kind of "fmap".

hvr updated this revision to Diff 326.Aug 11 2014, 1:34 PM
hvr edited edge metadata.

fixed register-usage

rwbarton accepted this revision.Aug 11 2014, 1:39 PM
rwbarton edited edge metadata.

Whoops, Build B394: Diff 326 (D141) has failed! Full logs available at F12428.

Yay! Build B394: Diff 326 (D141) has succeeded! Full logs available at F12472.

hvr retitled this revision from Add bit scan {forward,reverse} insns to x86 NCG to Add bit scan {forward,reverse} & CMOVcc insns to x86 NCG.Aug 12 2014, 7:52 AM
hvr updated this object.
hvr edited the test plan for this revision. (Show Details)
hvr edited edge metadata.
ezyang accepted this revision.Aug 12 2014, 7:55 AM
ezyang edited edge metadata.

OK, seems good.

compiler/nativeGen/X86/Instr.hs
530

Probably want to do this strictly.

austin accepted this revision.Aug 12 2014, 8:40 AM
austin edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Aug 12 2014, 8:40 AM
hvr closed this revision.Aug 12 2014, 8:58 AM
hvr updated this revision to Diff 333.

Closed by commit rGHC3669b60cb0b2 (authored by @hvr).

hvr closed this revision.Aug 12 2014, 8:58 AM
hvr updated this revision to Diff 334.

Closed by commit rGHC9f285fa40f6f (authored by @hvr).